Memory devices based on arrays of quantum dots are known. For example, “Nanocrystal Memory Cell Using High-Density Si0.73Ge0.27 Quantum Dot Array” by D-H. Chae et al., Journal of the Korean Physical Society, volume 35, pages S995 to S998 (1999) describes a metal-oxide-semiconductor field-effect transistor (MOSFET) in which silicon-germanium nanocrystals are incorporated into the gate oxide. “Memory Operation of Silicon Quantum-Dot Floating-Gate Metal-Oxide-Semiconductor Field-Effect Transistor” by A. Kohno et al., Japanese Journal of Applied Physics, volume 40, pages L721 to 723 (2001) describes a similar device in which silicon quantum dots are used. Another similar device is also described in US 2007/108502 A1.
In these types of devices, quantum dots are charged and discharged by electrons tunnelling to and from a channel through a thin gate oxide. Thus, write, erase and hold times depend on the thickness of the gate oxide. Therefore, although the gate oxide can be made thicker to increase the hold time, this also increases the write and erase times. Moreover, a thicker gate oxide tends to require larger write and erase voltages.
Another significant drawback of these types of device is that the gate oxide tends to degrade with use.
Similar, but more complex, memory devices have also been proposed. For example, U.S. Pat. No. 5,905,273 A describes a field-effect transistor having three-dimensional array of quantum dots comprising indium arsenide (InAs) embedded in a layer of aluminium gallium arsenide (AlGaAs) lying between a gallium arsenide (GaAs) channel and a gate electrode. In this device, electrons can tunnel between quantum dots.
In this type of device too, operation involves tunnelling between quantum dots and, thus, regions of AlGaAs between quantum dots are also liable to degrade with use. Generally, these memory devices tend to require high voltages to operate. For example, source and drain voltages of a few volts and gate voltages of the order of magnitude of 10 V are common.
Moreover, if a memory device is found not to operate properly due to, for example, misalignment or stray impurities, then there is little, if any, scope for repairing the device.
Although these types of devices can be fabricated using quantum dots which arrange themselves into an array, control over the position of quantum dots is limited.
One solution is to use high-resolution fabrication processes, such as a electron-beam lithography, focused ion-beam milling or focussed ion-beam implantation, to define the position (or intended position) of dots.
For instance, “Electrochemical growth of Co nanodots on patterned Si substrates” by M. V. Rastei et al., Applied Physics Letters, volume 85, pages 2050 to 2052 (2004) describes prestructuring a silicon substrate and using the prestructured substrate as a nano-electrode template to perform a selective electrodeposition of cobalt nanodots. “Dot-array implantation for patterned doping of semiconductors” by H. D. Wanzenboeck et al., Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms, volume 242, page 257 (2006) describes doping silicon with a focused ion beam.
However, these techniques tend not to be particularly suited to forming arrays on a large scale. For example, the maximum storage density is limited to about 1010 bits/cm2. Moreover, dots formed using focused ion-beam implantation tend to contain about 105 ions per dot. It is desirable to reduce the number of ions per dot.